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318589-005

Quad-Core Intel® Xeon® Processor

5400 Series

Datasheet

August 2008

Summary of content (118 pages)

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Quad-Core Intel® Xeon® Processor 5400 Series Datasheet August 2008 318589-005
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ..................................................................................................... 10 1.2 State of Data .................................................................................................... 13 1.3 References .......................................................................................................
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6.3 6.2.1 Intel® Thermal Monitor Features...............................................................90 6.2.2 On-Demand Mode ...................................................................................92 6.2.3 PROCHOT# Signal ..................................................................................93 6.2.4 FORCEPR# Signal ...................................................................................93 6.2.5 THERMTRIP# Signal ..........................................................
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Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 3-1 3-2 3-3 3-4 3-5 3-6 3-7 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 7-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 Input Device Hysteresis ..................................................................................... 25 Quad-Core Intel® Xeon® Processor X5482 Load Current versus Time ...................... 30 Quad-Core Intel® Xeon® Processor X5400 Series Load Current versus Time ............
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Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 3-1 3-2 3-3 4-1 4-2 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 7-1 7-2 8-1 8-2 8-3 6 Quad-Core Intel® Xeon® Processor 5400 Series ...................................................10 Core Frequency to FSB Multiplier Configuration ......................................................17 BSEL[2:0] Frequency Table .................................................................................
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Revision History Revision Description Date 001 Initial release 002 Added product information for the Quad-Core Intel® Xeon® Processor L5408. November 2007 March 2008 003 Added product information for the Quad-Core Intel® Xeon® Processor L5400 Series. April 2008 004 Corrected L1 cache size Introduced X5492 Updated X5482 power levels on E-step August 2008 005 Maintains change bars from version 004. Denoted in the Introduction section that E-step of the X5482 falls into the 120W X5400 family.
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Quad-Core Intel® Xeon® Processor 5400 Series Datasheet
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1 Introduction The Quad-Core Intel® Xeon® Processor 5400 Series is a server/workstation processor utilizing four 45-nm Hi-k next generation Intel® Core™ microarchitecture cores. The processor is manufactured on Intel’s 45 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. The QuadCore Intel® Xeon® Processor 5400 Series maintains the tradition of compatibility with IA-32 software.
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solutions. Intel Virtualization Technology is used in conjunction with Virtual Machine Monitor software enabling multiple, independent software environments inside a single platform. Further details on Intel Virtualization Technology can be found at http://developer.intel.com/technology/platform-technology/virtualization/index.htm. The Quad-Core Intel® Xeon® Processor 5400 Series is intended for high performance server and workstation systems.
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Commonly used terms are explained here for clarification: • Quad-Core Intel® Xeon® Processor 5400 Series - Intel 64-bit microprocessor intended for dual processor servers and workstations based on Intel’s 45 nanometer process, in the PC-LGA 771 package with four processor cores. For this document “processors” is used as the generic term for the “Quad-Core Intel® Xeon® Processor 5400 Series”.
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• Processor core – Processor core with integrated L1 cache. L2 cache and system bus interface are shared between the two cores on the die. All AC timing and signal integrity specifications are at the pads of the system bus interface. • Front Side Bus (FSB) – The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions, as well as interrupt messages, pass between the processor and chipset over the FSB.
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• VRM (Voltage Regulator Module) – DC-DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and current to the processor based on the logic state of the processor VID bits. • EVRD (Enterprise Voltage Regulator Down) – DC-DC converter integrated onto the system board that provides the correct voltage and current to the processor based on the logic state of the processor VID bits. • VCC – The processor core power supply. • VSS – The processor ground.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.1 Front Side Bus and GTLREF Most Quad-Core Intel® Xeon® Processor 5400 Series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.2 Power and Ground Lands For clean on-chip processor core power distribution, the processor has 223 VCC (power) and 267 VSS (ground) inputs. All VCC lands must be connected to the processor power plane, while all VSS lands must be connected to the system ground plane. The processor VCC lands must be supplied with the voltage determined by the processor Voltage IDentification (VID) signals. See Table 2-3 for VID definitions.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous processor generations, the Quad-Core Intel® Xeon® Processor 5400 Series core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during manufacturing. The default setting is for the maximum speed of the processor.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-2. 2.4.2 BSEL[2:0] Frequency Table BSEL2 BSEL1 BSEL0 Bus Clock Frequency 0 0 0 266.66 MHz 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 333.33 MHz 1 0 1 Reserved 1 1 0 400 MHz 1 1 1 Reserved PLL Power Supply An on-die PLL filter solution is implemented on the Quad-Core Intel® Xeon® Processor 5400 Series.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The Quad-Core Intel® Xeon® Processor 5400 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (VCC). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-3. Voltage Identification Definition HEX VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX HEX VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 7A 1 1 1 1 0 1 0.8500 3C 0 1 1 1 1 0 1.2375 78 1 1 1 1 0 0 0.8625 3A 0 1 1 1 0 1 1.2500 76 1 1 1 0 1 1 0.8750 38 0 1 1 1 0 0 1.2625 74 1 1 1 0 1 0 0.8875 36 0 1 1 0 1 1 1.2750 72 1 1 1 0 0 1 0.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-4. Loadline Selection Truth Table for LL_ID[1:0] LL_ID1 LL_ID0 0 0 Reserved 0 1 Dual-Core Intel® Xeon® Processor 5100 series, Dual-Core Intel® Xeon® Processor 5200 Series, and Quad-Core Intel® Xeon® Processor 5400 Series 1 0 Reserved 1 1 Quad-Core Intel® Xeon® processor 5300 series Note: Table 2-5. The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The TESTHI signals must use individual pull-up resistors as detailed below. A matched resistor must be used for each signal: • TESTHI10 – cannot be grouped with other TESTHI signals • TESTHI11 – cannot be grouped with other TESTHI signals • TESTHI12 - cannot be grouped with other TESTHI signals 2.7 Front Side Bus Signal Groups The FSB signals have been combined into groups by buffer type.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-6.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.8 CMOS Asynchronous and Open Drain Asynchronous Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#, and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-10. PECI DC Electrical Limits Notes1 Symbol Definition and Conditions Min Max Units Vin Input Voltage Range -0.150 VTT V Vhysteresis Hysteresis 0.1 * VTT N/A V Vn Negative-edge threshold voltage 0.275 * VTT 0.500 * VTT V Vp Positive-edge threshold voltage 0.550 * VTT 0.725 * VTT V Isource High level output source (VOH = 0.75 * VTT) -6.0 N/A mA Isink Low level output sink (VOL = 0.25 * VTT) 0.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.11 Mixing Processors Intel supports and validates dual processor configurations only in which both processors operate with the same FSB frequency, core frequency, power segments, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel. Combining processors from different power segments is also not supported.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-11. Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit V VCC Core voltage with respect to VSS -0.30 1.35 VTT FSB termination voltage with respect to VSS -0.30 1.45 V TCASE Processor case temperature See Chapter 6 See Chapter 6 °C TSTORAGE Storage temperature -40 85 °C Notes1, 2 3, 4, 5 Notes: 1.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-12. Voltage and Current Specifications (Sheet 1 of 2) Symbol 28 Parameter Min VID VID range VCC VCC for processor core Launch - FMB Vcc_boot Default VCC Voltage for initial power up VVID_STEP VID step size during a transition VVID_SHIFT Total allowable DC load line shift from VID steps VTT FSB termination voltage (DC + AC specification) 1.045 VCCPLL PLL supply voltage (DC + AC specification) 1.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-12.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. The voltage specification requirements are measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-3. Quad-Core Intel® Xeon® Processor X5400 Series Load Current versus Time Sustained Current (A) 13 0 12 5 12 0 115 110 10 5 10 0 0 .0 1 0 .1 1 10 10 0 10 0 0 Tim e Duration (s) Notes: 1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-5. Quad-Core Intel® Xeon® Processor L5400 Series Load Current versus Time Sustained Current (A) 70 65 60 55 50 45 40 0 .0 1 0 .1 1 10 10 0 10 0 0 Time Duration (s) Notes: 1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization. Table 2-13.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-13. Quad-Core Intel® Xeon® Processor X5482 VCC Static and Transient Tolerance (Sheet 2 of 2) ICC (A) VCC_Max (V) VCC_Typ (V) VCC_Min (V) Notes 120 VID - 0.150 VID - 0.160 VID - 0.170 1,2,3 125 VID - 0.156 VID - 0.166 VID - 0.176 1,2,3 130 VID - 0.163 VID - 0.173 VID - 0.183 1,2,3 135 VID - 0.169 VID - 0.179 VID - 0.189 1,2,3 140 VID - 0.175 VID - 0.185 VID - 0.195 1,2,3 145 VID - 0.181 VID - 0.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-14. Quad-Core Intel® Xeon® Processor X5400 Series, Quad-Core Intel® Xeon® Processor E5400 Series, Quad-Core Intel® Xeon® Processor L5400 Series VCC Static and Transient Tolerance (Sheet 2 of 2) ICC (A) VCC_Max (V) VCC_Typ (V) VCC_Min (V) Notes 110 VID - 0.138 VID - 0.153 VID - 0.168 1, 2, 3, 4, 5, 6 115 VID - 0.144 VID - 0.159 VID - 0.174 1, 2, 3, 4, 5, 6 120 VID - 0.150 VID - 0.165 VID - 0.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Quad-Core Intel® Xeon® Processor X5482 VCC Static and Transient Tolerance Load Lines Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 VID - 0.000 VID - 0.050 VCC Maximum VID - 0.100 Vcc [V] Figure 2-7. VID - 0.150 VCC Typical VID - 0.200 VCC Minimum VID - 0.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-8. Quad-Core Intel® Xeon® Processor X5400 Series VCC Static and Transient Tolerance Load Lines Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 VID - 0.000 VID - 0.020 VID - 0.040 VCC Maximum VID - 0.060 Vcc [V] VID - 0.080 VID - 0.100 VCC Minimum VID - 0.120 VID - 0.140 VCC Typical VID - 0.160 VID - 0.180 VID - 0.200 Figure 2-9.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-10. Quad-Core Intel® Xeon® Processor L5400 Series VCC Static and Transient Tolerance Load Lines Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 VID - 0.000 VID - 0.020 VCC Maximum Vcc [V] VID - 0.040 VID - 0.060 VID - 0.080 VCC Typical VID - 0.100 VCC Minimum VID - 0.120 Notes: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.13.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-16. CMOS Signal Input/Output Group and TAP Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 VIL Input Low Voltage -0.10 0.00 0.3 * VTT V 2,3 VIH Input High Voltage 0.7 * VTT VTT VTT + 0.1 V 2 VOL Output Low Voltage -0.10 0 0.1 * VTT V 2 VOH Output High Voltage 0.9 * VTT VTT VTT + 0.1 V 2 IOL Output Low Current 1.70 N/A 4.70 mA 4 IOH Output High Current 1.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-11. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID Notes: 1. VOS is the measured overshoot voltage. 2. TOS is the measured time duration above VID. 2.13.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard using high precision voltage divider circuits. Refer to the appropriate platform design guidelines for implementation details. Table 2-19. AGTL+ Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes1 GTLREF_DATA_MID, GTLREF_DATA_END Data Bus Reference Voltage 0.98 * 0.667 * VTT 0.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 9. VHavg can be measured directly using “Vtop” on Agilent and “High” on Tektronix oscilloscopes. 10. For VIN between 0 V and VH. 11.
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-14. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 250 + 0.5 (VHavg - 700) 350 300 250 250 mV 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 2-15.
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Mechanical Specifications 3 Mechanical Specifications The Quad-Core Intel® Xeon® Processor 5400 Series is packaged in a Flip Chip Land Grid Array (FC-LGA) package that interfaces to the baseboard via a LGA771 socket. The package consists of a processor core mounted on a pinless substrate with 771 lands. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink.
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Mechanical Specifications Figure 3-2. Note: 44 Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 1 of 3) Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution are available in the processor Thermal/Mechanical Design Guidelines.
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Mechanical Specifications Figure 3-3.
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Mechanical Specifications Figure 3-4. Note: 46 Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 3 of 3) The optional dimple packing marking highlighted by Detail F from the above drawing may only be found on initial processors.
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Mechanical Specifications 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. Decoupling capacitors are typically mounted to either the topside or landside of the package substrate. See Figure 3-4 for keepout zones. 3.3 Package Loading Specifications Table 3-1 provides dynamic and static load specifications for the processor package.
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Mechanical Specifications 3.4 Package Handling Guidelines Table 3-2 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 3-2. Package Handling Guidelines Parameter Maximum Recommended Units Notes Shear 311 70 N lbf 1,4,5 Tensile 111 25 N lbf 2,4,5 Torque 3.95 35 N-m LBF-in 3,4,5 Notes: 1.
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Mechanical Specifications Figure 3-5. Processor Top-side Markings (Example) GROUP1LINE1 GROUP1LINE2 GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 Legend: Mark Text (Production Mark): GROUP1LINE1 GROUP1LINE2 GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 3200DP/12M/1600 Intel ® Xeon ® Proc# SXXX COO i (M) © ‘07 FPO ATPO S/N Note: 3.9 2D matrix is required for engineering samples only (encoded with ATPO-S/N).
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Mechanical Specifications Figure 3-7.
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Land Listing 4 Land Listing 4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by land number. 4.1.1 Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 1 of 20) Pin Name Pin No. Signal Buffer Type Direction Table 4-1.
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Land Listing Table 4-1. Pin Name BSEL0 Land Listing by Land Name (Sheet 3 of 20) Pin No. G29 Signal Buffer Type CMOS ASync Direction Table 4-1. Pin Name Land Listing by Land Name (Sheet 4 of 20) Pin No.
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Land Listing Table 4-1. Land Listing by Land Name (Sheet 5 of 20) Pin Name Pin No. DP2# H16 DP3# DRDY# Signal Buffer Type Direction Table 4-1. Pin Name Land Listing by Land Name (Sheet 6 of 20) Pin No.
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Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 7 of 20) Pin No. Signal Buffer Type Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 8 of 20) Pin No.
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Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 9 of 20) Pin No. Signal Buffer Type Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 10 of 20) Pin No.
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Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 11 of 20) Pin No. Signal Buffer Type Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 12 of 20) Pin No.
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Land Listing Table 4-1. Land Listing by Land Name (Sheet 13 of 20) Pin Name Pin No. Signal Buffer Type Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 14 of 20) Pin No.
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Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 15 of 20) Pin No. VSS AF29 VSS VSS VSS VSS Signal Buffer Type Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 16 of 20) Pin No.
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Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 17 of 20) Pin No. Signal Buffer Type Table 4-1. Direction Pin Name VSS B11 Power/Other VSS VSS B14 Power/Other VSS B17 Power/Other VSS B20 VSS B24 VSS VSS Land Listing by Land Name (Sheet 18 of 20) Pin No.
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Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 19 of 20) Pin No. Signal Buffer Type Table 4-1. Direction Land Listing by Land Name (Sheet 20 of 20) Pin Name Pin No.
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Land Listing 4.1.2 Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 1 of 20) Pin No. A10 Pin Name D08# Signal Buffer Type Source Sync Direction Table 4-2. Pin No.
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Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 3 of 20) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
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Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 5 of 20) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
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Land Listing Table 4-2. Pin No. AJ9 Land Listing by Land Number (Sheet 7 of 20) Pin Name VCC Signal Buffer Type Direction Power/Other Table 4-2. Pin No.
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Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 9 of 20) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
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Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 11 of 20) Pin Name Signal Buffer Type C2 BNR# Common Clk C20 DBI3# C21 D58# C22 VSS Power/Other C23 RESERVED Direction Table 4-2. Pin No.
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Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 13 of 20) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
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Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 15 of 20) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
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Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 17 of 20) Pin Name Signal Buffer Type Direction M28 VCC Power/Other M29 VCC Power/Other M3 STPCLK# CMOS Async M30 VCC Power/Other M4 A07# Source Sync Input/Output Input Table 4-2. Pin No.
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Land Listing Table 4-2. Pin No. U28 Land Listing by Land Number (Sheet 19 of 20) Pin Name VCC Signal Buffer Type Direction Power/Other U29 VCC Power/Other U3 AP1# Common Clk Table 4-2. Pin No.
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Signal Definitions 5 Signal Definitions 5.1 Signal Definitions Table 5-1. Signal Definitions (Sheet 1 of 8) Name A[37:3]# Type Description Notes 238-byte I/O A[37:3]# (Address) define a physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins of all agents on the FSB. A[37:3]# are protected by parity signals AP[1:0]#.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 2 of 8) Name Type Description I The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 3 of 8) Name Type Description BSEL[2:0] O The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 2-2 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processors, chipset, and clock synthesizer. All FSB agents must operate at the same frequency.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 4 of 8) Name DEFER# Description Notes I DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or I/O agent. This signal must connect the appropriate pins of all processor FSB agents. 3 DP[3:0]# I/O DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 5 of 8) Name GTLREF_DATA_MID GTLREF_DATA_END Type Description Notes I GTLREF_DATA determines the signal reference level for AGTL+ data input lands. GTLREF_DATA is used by the AGTL+ receivers to determine if a signal is a logical 0 or a logical 1. Please refer to Table 2-19 and the appropriate platform design guidelines for additional details.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 6 of 8) Name MCERR# 76 Type Description I/O MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor FSB agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: • Enabled or disabled. • Asserted, if configured, for internal errors along with IERR#.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 7 of 8) Name Type Description RSP# I RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor FSB agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 8 of 8) Name Type Description TMS I TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. See the Debug Port Design Guide for Intel® 5000 Series Chipset Memory Controller Hub (MCH) Systems (External Version) for further information. TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer.
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Thermal Specifications 6 Thermal Specifications 6.1 Package Thermal Specifications The Quad-Core Intel® Xeon® Processor 5400 Series requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
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Thermal Specifications Processor Thermal Features). Systems that implement fan speed control must be designed to use this data. Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications.
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Thermal Specifications power dissipation is currently planned. Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2 feature must be enabled for the processor to remain within its specifications. Table 6-1. Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step) Thermal Specifications Core Frequency Launch to FMB Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes 150 (X5492 and X5482 C-step) 5 See Figure 6-1; Table 6-2 1,2,3,4,5,6 Notes: 1.
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Thermal Specifications Table 6-2. 82 Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile Table Power (W) TCASE_MAX (°C) 0 35.0 5 35.9 10 36.9 15 37.8 20 38.7 25 39.7 30 40.6 35 41.5 40 42.5 45 43.0 50 44.4 55 45.3 60 46.2 65 47.2 70 48.1 75 49.0 80 50.0 85 50.9 90 51.8 95 52.8 100 53.7 105 54.6 110 55.6 115 56.5 120 57.4 125 58.4 130 59.3 135 60.2 140 61.2 145 62.1 150 63.
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Thermal Specifications Table 6-3. Quad-Core Intel® Xeon® Processor X5400 Series Thermal Specifications Core Frequency Launch to FMB Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) 120 5 See Figure 6-2; Table 6-4; Table 6-5 Notes 1, 2, 3, 4, 5 Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC.
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Thermal Specifications Table 6-4. 84 Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile A Table Power (W) TCASE_MAX (°C) 0 42.8 5 43.6 10 44.5 15 45.3 20 46.2 25 47.0 30 47.8 35 48.7 40 49.5 45 50.0 50 51.2 55 52.0 60 52.9 65 53.7 70 54.6 75 55.4 80 56.2 85 57.1 90 57.9 95 58.8 100 59.6 105 60.4 110 61.3 115 62.1 120 63.
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Thermal Specifications Table 6-5. Table 6-6. Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile B Table Power (W) TCASE_MAX (°C) 0 43.5 5 44.6 10 45.7 15 46.8 20 47.9 25 49.0 30 50.1 35 51.2 40 52.3 45 53.4 50 54.6 55 55.7 60 56.8 65 57.9 70 59.0 75 60.1 80 61.2 85 62.3 90 63.4 95 64.5 100 65.6 105 66.7 110 67.8 115 68.9 120 70.
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Thermal Specifications Figure 6-3. Quad-Core Intel® Xeon® Processor E5400 Series Thermal Profile 70 68 66 64 62 60 Tcase [C] 58 56 54 52 Thermal Profile Y = 0.298*x + 43.2 50 48 46 44 42 40 0 10 20 30 40 50 60 70 80 Pow e r [W] Notes: 1. Please refer to Table 6-7 for discrete points that constitute the thermal profile. 2. Implementation of the Quad-Core Intel® Xeon® Processor 5400 Series Thermal Profile should result in virtually no TCC activation.
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Thermal Specifications Table 6-7. Table 6-8. Quad-Core Intel® Xeon® Processor E5400 Series Thermal Profile Table (Sheet 2 of 2) Power (W) TCASE_MAX (°C) 70 64.1 75 65.6 80 67.0 Quad-Core Intel® Xeon® Processor L5400 Series Thermal Specifications Core Frequency Launch to FMB Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes 50 5 See Figure 6-4; Table 6-9 1, 2, 3, 4, 5 Notes: 1. These values are specified at VCC_MAX for all processor frequencies.
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Thermal Specifications Table 6-9. Quad-Core Intel® Xeon® Processor L5400 Series Thermal Profile Table Power (W) TCASE_MAX (°C) 0 42.1 5 43.6 10 45.1 15 46.6 20 48.1 25 49.6 30 51.0 35 52.5 40 54.0 45 55.5 50 57.0 Table 6-10. Quad-Core Intel® Xeon® Processor L5408 Thermal Specifications Core Frequency Launch to FMB Notes: 1. 2. 3. 4. 5.
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Thermal Specifications Figure 6-5. Quad-Core Intel® Xeon® Processor L5408 Thermal Profile Thermal Profile 90 Tcase [C] 80 Short-term Thermal Profile may only be used for short term excursions to higher ambient temperatures, not to exceed 360 hours per year 70 Short-Term Thermal Profile Tc = 0.678 * P + 60 60 Nominal Thermal Profile Tc = 0.678 * P + 45 50 40 0 5 10 15 20 25 30 35 40 Power [W] Notes: 1. Please refer to Table 6-11 for discrete points that constitute the thermal profile. 2.
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Thermal Specifications 6.1.2 Thermal Metrology The minimum and maximum case temperatures (TCASE) are specified in Table 6-2, Table 6-4, Table 6-5, and Table 6-7, and Table 6-9 and Table 6-11 are measured at the geometric top center of the processor integrated heat spreader (IHS). Figure 6-6 illustrates the location where TCASE temperature measurements should be made.
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Thermal Specifications needed by modulating (starting and stopping) the internal processor core clocks. The temperature at which the Intel® Thermal Monitor 1 activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active.
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Thermal Specifications The second operating point consists of both a lower operating frequency and voltage. The lowest operating frequency is determined by the lowest supported bus ratio (1/6 for the Quad-Core Intel® Xeon® Processor 5400 Series). When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs rapidly, on the order of 5 µs.
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Thermal Specifications Series must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a ‘1’, the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same IA32_CLOCK_MODULATION MSR.
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Thermal Specifications 6.2.5 THERMTRIP# Signal Regardless of whether or not Intel® Thermal Monitor 1 or Intel® Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 5-1). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 5-1.
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Thermal Specifications should utilize the relative temperature value delivered over PECI in conjunction with the TCONTROL MSR value to control or optimize fan speeds. Figure 6-9 shows a conceptual fan control diagram using PECI temperatures. The relative temperature value reported over PECI represents the data below the onset of thermal control circuit (TCC) activation as needed by PROCHOT# assertions. As the temperature approaches TCC activation, the PECI value approaches zero.
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Thermal Specifications 6.3.2 PECI Specifications 6.3.2.1 PECI Device Address The PECI device address for socket 0 is 0x30 and socket 1 is 0x31. Please note that each address also supports two domains (Domain0 and Domain1). For more information on PECI domains, please refer to the Platform Environment Control Interface (PECI) Specification. 6.3.2.2 PECI Command Support PECI command support is covered in detail in Platform Environment Control Interface Specification.
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Features 7 Features 7.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Quad-Core Intel® Xeon® Processor 5400 Series samples its hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifics on these options, please refer to Table 7-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
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Features 7.2.1 Normal State This is the normal operating state for the processor. 7.2.2 HALT or Extended HALT State The Extended HALT state (C1E) is enabled via the BIOS. The Extended HALT state must be enabled for the processor to remain within its specifications. The Extended HALT state requires support for dynamic VID transitions in the platform. 7.2.2.1 HALT State HALT is a low power state entered when the processor have executed the HALT or MWAIT instruction.
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Features Table 7-2.
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Features Figure 7-1.
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Features While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal state. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus. The PBE# signal can be driven when the processor is in Stop-Grant state.
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Features Enhanced Intel SpeedStep Technology creates processor performance states (P-states) or voltage/frequency operating points which are lower power capability states within the Normal state (see Figure 7-1 for the Stop Clock State Machine for supported Pstates). Enhanced Intel SpeedStep Technology enables real-time dynamic switching between frequency and voltage points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage.
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Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Quad-Core Intel® Xeon® Processor 5400 Series will be offered as an Intel boxed processor.
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Boxed Processor Specifications Figure 8-1. Boxed Quad-Core Intel® Xeon® Processor 5400 Series 1U Passive/3U+ Active Combination Heat Sink (With Removable Fan) Figure 8-2.
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Boxed Processor Specifications Figure 8-3. 2U Passive Quad-Core Intel® Xeon® Processor 5400 Series Thermal Solution (Exploded View) Notes: 1. The heat sinks represented in these images are for reference only, and may not represent the final boxed processor heat sinks. 2. The screws, springs, and standoffs will be captive to the heat sink. This image shows all of the components in an exploded view. 3. It is intended that the CEK spring will ship with the base board and be pre-attached prior to shipping.
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Boxed Processor Specifications Figure 8-4.
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Boxed Processor Specifications Figure 8-5.
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Boxed Processor Specifications Figure 8-6.
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Boxed Processor Specifications Figure 8-7.
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Boxed Processor Specifications Figure 8-8.
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Boxed Processor Specifications Figure 8-9.
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Boxed Processor Specifications Figure 8-10.
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Boxed Processor Specifications 8.2.2 Boxed Processor Heat Sink Weight 8.2.2.1 Thermal Solution Weight The 1U passive/3U+ active combination heat sink solution and the 2U passive heat sink solution will not exceed a mass of 1050 grams. Note that this is per processor, a dual processor system will have up to 2010 grams total mass in the heat sinks. This large mass will require a minimum chassis stiffness to be met in order to withstand force during shock and vibration.
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Boxed Processor Specifications The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan power header identification and location must be documented in the suppliers platform documentation, or on the baseboard itself. The baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket. Table 8-1. Table 8-2.
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Boxed Processor Specifications around the heatsink. It is assumed that a 40°C TLA is met. This requires a superior chassis design to limit the TRISE at or below 5°C with an external ambient temperature of 35°C. These specifications apply to both copper and aluminum heatsink solutions. Following these guidelines allows the designer to meet Quad-Core Intel® Xeon® Processor 5400 Series Thermal Profile and conform to the thermal requirements of the processor. 8.3.2.
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Boxed Processor Specifications § 116
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Debug Tools Specifications 9 Debug Tools Specifications Please refer to the appropriate platform design guidelines for information regarding debug tool specifications. Section 1.3 provides collateral details. 9.1 Debug Port System Requirements The Quad-Core Intel® Xeon® Processor 5400 Series debug port is the command and control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of the processors for system debug.
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Debug Tools Specifications 9.3.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI plugs into the socket, while the processor plugs into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor.