XB112– Product Brief XB112 Breakout Board Product Brief Page 1 of 23 Proprietary and Confidential © 2018 by Acconeer – All rights reserved 2018-12-21
XB112 Breakout Board Product Brief Proprietary and Confidential Author: Acconeer Version 1.
Table of Contents 1 Introduction ..................................................................................................................................... 4 2 XB112 Breakout Board ................................................................................................................... 5 2.1 Overview ................................................................................................................................. 5 2.2 Power .........................................
1 Introduction This document describes the Acconeer XB112 breakout board for the XM112 module. It has been designed with the purpose of flashing, debugging and supplying power to the Acconeer XM112 Module.
2 XB112 Breakout Board 2.1 Overview The XB112 breakout board for the XM112 module is designed to make the interfaces from the XM112 module accessible for evaluation and debug. It also enables flashing of the XM112 via USBUART or SW-DP. The XM112 is connected to the XB112 via a board-to-board connector on the top side of the PCB. In addition to the board-to-board connector for the XM112, the XB112 comprises two USB connectors, two 2x5 pin headers and one not mounted 2x20 pin header.
The thickness of the PCB is 1.2 mm. The block diagram of XB112 is found in Figure 1 below. 1.8V USB Connector 1 ERASE Button NRST Button ERASE NRST FTDI FT230XS Dual LDO UART0 1.8V UART2 MCU_INT MCU_GPIO Switched Power Regulator 1.8V USB Connector 2 JTAG/SWD pin header Board to board connector UART4 Misc GPIO pin header I2C MCU_INT MCU_GPIO 40-pin connector (NM) 1.8V SWD FTDI FT4222H 5V Figure 1. The block diagram of XB112 radar module breakout board. 2.
USB Connector 1 gate (U3) which in turn enables the switched power regulator. “CBUS0” is configured as “BCDCHARGER#” and “CBUS1” is configured as “PWREN#” as default. CBUS0 CBUS1 USB BCDCHARGER# A PWREN# FTDI FT230XS NAND Y ENABLE GATE B Switched Power Regulator 1.8V Truth table A 0 1 0 1 B 0 0 1 1 Y 1 1 1 0 Figure 2. Block Diagram showing the logic control of the Switched Power Regulator ENABLE signal. “BCDCHARGER#” will output a logic “0” if a USB Dedicated Charger is detected on USB1.
2.3.2 USB2 (J2) USB2 is used for high speed data output from the module SPI interface. It is converted to USB via the FTDI chip FT4222H. The pinout of USB2 is shown in Table 2. Table 2. The pinout of J2. Pin Number Signal 1 VBUS 2 D- 3 D+ 4 ID (GND) 5 GND 2.3.3 2x20 pin header (J3) The 2x20 pin header (1.27mm pitch) is not mounted. The reason is that it is intended for Acconeer internal use only. All the interfaces available in the 2x20 pin header are also available in the other connectors.
2.3.4 30 pin board-to-board connector (J4) The 30-pin board-to-board connector is intended to connect the XM112 to the XB112. The pinout is found in Table 4. Table 4. The pinout of J4.
2.3.6 2x5 pin header (J6) The 2x5 pin header (1.27mm pitch) contains miscellaneous 1.8V signals from the XM112. The pinout is found in Table 6. Table 6. The pinout of J6. Pin Number Signal Pin Number Signal 1 1.8V 2 I2C_SCL 3 MCU_INT 4 I2C_SDA 5 MCU_GPIO 6 UART4_TXRX1 7 UART2_RXTX1 8 UART4_RXTX1 9 UART2_TXRX1 10 GND 2.4 Buttons There are two buttons on the XB112. J7 controls the signal “ERASE” from XM112 and J8 controls “NRST” from the XM112.
Except for the UART interface there are four GPIOs on the FT230XS. The usage and XB112 default configuration of the GPIOs are listed in Table 9. The GPIOs can be flashed via the USB interface by using the program FTPROG from FTDI. For details, refer to the FT230XS datasheet [1]. Table 9. The FT230XS GPIOs. FT230XS Pin Name XB112 Usage Comment CBUS0 BCDCHARGER# Will output “0” if a USB dedicated charger is detected on USB1.
FT4222H Pin Name XB112 Connection Comment ATSAME70 on XM112. SS0O SPI_SS Connected to SPI0_NPCS0 on ATSAME70 on XM112. Except for the SPI interface there are four GPIOs on the FT4222H. The usage and XB112 default configuration of the GPIOs are listed in Table 11. The GPIOs can be controlled via an API provided by FTDI. For details regarding the FT4222H GPIO control, refer to the datasheet [2]. Table 11. The FT4222H GPIOs.
XB112– Product Brief 2.
2.8 Component Placement Drawing The component placement drawing of XB112 is found below.
Page 18 of 23 Proprietary and Confidential © 2018 by Acconeer – All rights reserved 2018-12-21
2.9 Bill of Material Table 12 shows the BOM for XB112. Table 12. The BOM of XB112. Component Ref.
U4 FT230XS-R/USB to UART bridge 1 U5 FT4222H/USB to SPI bridge 1 J5,J6 FTSH_105_04_F_DH/SWD 2 Connector, Right angle 2x5 pin header J7,J8 SWITCH TACTILE SPSTNO 0.
References 1. FT230XS datasheet: https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT230X.pdf 2. FT4222H datasheet: https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT4222H.
3 Revision History Date 2018-12-19 Version 1.
4 Disclaimer The information herein is believed to be correct as of the date issued. Acconeer AB (“Acconeer”) will not be responsible for damages of any nature resulting from the use or reliance upon the information contained herein. Acconeer makes no warranties, expressed or implied, of merchantability or fitness for a particular purpose or course of performance or usage of trade.
