Data Sheet

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Habanero

Data Sheet

• Wi-Fi 5 (802.11a/n/ac Wave2) 5GHz with 2x2 MU-MiMo, 866.7Mbps data-rate

• Wi-Fi 5 (802.11b/g/n/ac) 2.4GHz, 400Mbps data-rate

• MIPI DBI v2.0 type B interface

• CPU - IPQ4019/IPQ4029 ( 716.8MHz)

• OpenWRTLinuxashimage

• 24-25dBmperchainRFoutputpower

• Size-45by49mm

• Available interfaces – 46 x GPIO, 1 x PCie 2.0, 1 x USB3.0, 1 x USB2.0,

2 x UART, 1 x SPI, 2 x I2C, 4 x PWM, 1 x JTAG, 1 x I2S/TDM,

5 x 1000/100/10 ethernets, 1 x RGMII, 1 x SDIO3.0/eMMC and parallels

 forNANDashmemoryandLCDcontroller

Quick specs

Habanerosystemonmodule(SOM)isbasedonanIPQ4019/IPQ4029SoCfromQualcomm,which

incorporates a powerful quad-core ARM Cortex A7 processor with NEON and FPU. It is ideal

forresourcedemandingapplicationsincludingrouters,gatewaysandaccesspoints.Habanero

comeswithahigh-power,dual-bandconcurrentradiosupporting802.11acWave2technology(2x2

MiMo). QCA8075C PHY gives support to 5 x Gigabit Ethernet ports. It also has 1 x USB3.0 and 1

xUSB2.0portsandsupportsothermiscellaneousinterfaces,whichcanbeconguredasgeneral-

purpose I/O pins. Hardware based NAT engine and security features like crypto engine, secure

bootmakeitidealforhigh-end,fastandsecurenetworkingapplications.Habanerocomesin

commercialandindustrialtemperatureversions.Commercialtemperaturerange:0-65°C,industrial

temperaturerange:-40-85°C.

Summary of content (35 pages)

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Habanero Data Sheet Habanero system on module (SOM) is based on an IPQ4019/IPQ4029 SoC from Qualcomm, which incorporates a powerful quad-core ARM Cortex A7 processor with NEON and FPU. It is ideal for resource demanding applications including routers, gateways and access points. Habanero comes with a high-power, dual-band concurrent radio supporting 802.11ac Wave2 technology (2x2 MiMo). QCA8075C PHY gives support to 5 x Gigabit Ethernet ports. It also has 1 x USB3.0 and 1 x USB2.
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Table of Contents 1. Product Overview 3 1.1 Features 3 2. Block diagram 4 3. Module pinout and Pin description 5 4. Electrical characteristics 16 5. Power management 16 5.1. Power consumption 16 6. Radio characteristics 17 7. Mechanical characteristics 18 8. Design considerations 18 8.1. Ethernet interface 19 8.2. USB 19 8.3. Parallel NAND flash / LCD 20 8.4. I2C 21 8.5. SD/eMMC 22 8.6. PCIe 23 8.7. JTAG 24 9. Thermal considerations 24 10. Development board 25 10.
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1. Features 1.1. Features TABLE 1-1. 8DEV6000 HABANERO FEATURES Feature list 8DEV6000 Habanero ARM Cortex-A7 IPQ4019/IPQ4029 Core type Integrated core Memory Core clock frequency 716.8MHz Cache 256KB L2 DRAM DDR3L 512MB (up to 1GB) NOR FLASH 32MB NAND FLASH (external) WIFI RF pin Display IEEE 802.11 b/g/n/ac 2x2 MU-MIMO 2.4GHz 20/40 MHz 256 QAM 2402-2482MHz 25dBm IEEE 802.
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2. Block diagram The following figure provides a basic overview of the 8DEV6000 Habanero module. FIGURE 2-1. 8DEV6000 HABANERO MODULE BLOCK DIAGRAM PCIe 8DEV6000 Habanero Module USB 3.0 2x RFFM8528 (5GHz Wi-fi PA) USB 2.0 2x RFFM8228 (2.4GHz Wi-fi PA) JTAG RGMII UART I2C Qualcomm IPQ4019/ IPQ4029 QCA8075C (5 port GEth PHY) DDR3L 512MB 48MHz Clock SPI Master I2S/TDM SDIO3.0/eMMC GPIO Ethernet SFP 2.
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3.
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TABLE 3-1. I/O DESCRIPTION (PAD TYPE) PARAMETERS Symbol Description AI Analog input AO Analog output GND Ground RF In/Out RF input/output I Digital input signal O Digital output signal IO Digital bidirectional signal OD Open drain TABLE 3-2. POWER, GROUND AND RESET Pin ID Pin name Type Description DVDD33 I 3.3V digital power DVDD_2.7V_Malibu O 2.
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TABLE 3-5. USB 3.0 Pin ID Pin name Type Description A60 USB1_DP AI, AO USB HS data positive B56 USB1_DM AI, AO USB HS data negative A59 USB1_SS_RX_P AI USB SS receive data positive B55 USB1_SS_RX_N AI USB SS receive data negative B53 USB1_SS_TX_P AO USB SS transmit data positive A56 USB1_SS_TX_N AO USB SS transmit data negative TABLE 3-6. USB 2.0 Pin ID Pin name Type Description B54 USB2_DP AI, AO USB HS data positive A58 USB2_DM AI, AO USB HS data negative TABLE 3-7.
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Pin ID Pin name Type Description A35 P2_TRX1+ AI, AO PHY2 MDI pair1 positive, connect to transformer B34 P2_TRX2- AI, AO PHY2 MDI pair2 negative, connect to transformer A36 P2_TRX2+ AI, AO PHY2 MDI pair2 positive, connect to transformer B35 P2_TRX3- AI, AO PHY2 MDI pair3 negative, connect to transformer A37 P2_TRX3+ AI, AO PHY2 MDI pair3 positive, connect to transformer A39 P3_TRX0- AI, AO PHY3 MDI pair0 negative, connect to transformer B36 P3_TRX0+ AI, AO PHY3 MDI pair0 posit
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TABLE 3-8.
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TABLE 3-9. GPIO Pin ID A8 Pin name GPIO CFG. FUNC_SEL Configurable Function Voltage 0 GPIO 3.3 1 BLSP_UART0_RXD 2 LED(0) GPIO16 Type Description I Rx data Led_clk or led_dar or led_strobe - A2 GPIO8 0 GPIO 3.3 1 BLSP_UART1_TXD O Tx data 2 WIFI0_UART_TXD O Wi-Fi UART output 3 WIFI1_UART_TXD O Wi-Fi UART output - A5 GPIO9 0 GPIO 3.
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Pin ID B11 A13 B12 A14 B13 A15 A16 B14 Habanero Pin name GPIO22 GPIO CFG. FUNC_SEL Configurable Function Voltage Type Description 0 GPIO 3.3 1 RGMII_RXD(0) 1.5(2.0)/2.5(1.0) I RGMII Data input 0 2 AUDIO_RXFSYNC(1) 3.0 I/O Left or Right indication of Audio I2S Rx interface and frame start indication of Audio TDM Rx interface 0 GPIO 3.3 1 SDIO_DAT(0) SDIO: 1.8/3.0; eMMC: 1.8 I/O SDIO Data input 0 2 RGMII_RXD(1) 1.5(2.0)/2.5(1.
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Pin ID A17 B15 A18 B17 A19 B18 A62 B58 A64 B59 Habanero Pin name GPIO CFG. FUNC_SEL Configurable Function Voltage 0 GPIO 3.3 1 SDIO_DAT(5) 2 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 Datasheet Type Description SDIO: 1.8/3.0; eMMC: 1.8 I/O SDIO Data input 5 RGMII_TXD(2) 1.5(2.0)/2.5(1.0) O RGMII Tx Data 2 3 AUDIO_PWM0 3.0 O Audio Pulse Width Modulation interface 0 0 GPIO 3.3 1 SDIO_DAT(6) SDIO: 1.8/3.0; eMMC: 1.
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Pin ID A63 Pin name GPIO CFG. FUNC_SEL Configurable Function Voltage 0 GPIO 3.3 1 RMII0_REFCLK 3.0 2 3 GPIO40 Type Description I/O Input reference clock when Slave mode. Output clock when Master mode WIFI0_RFSILIENT_BB(0) I Wi-Fi 0 RF silent signal (RF_Kill) WIFI1_RFSILIENT_BB(0) I Wi-Fi 1 RF silent signal (RF_Kill) - A65 GPIO41 5 LED(4) led_clk or led_dat or led_strobe 6 #PCIE_WAKEUP_N# 0 GPIO 3.3 1 RMII0_RXD(0) 3.
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Pin ID A74 B69 Pin name GPIO CFG. FUNC_SEL Configurable Function Voltage 0 GPIO 3.3 1 RMII1_DV 2 BLSP_SPI1_MISO 3 SMART_ANT7(0) 4 LED(8) 0 GPIO 3.3 1 RMII1_TX_EN 3.0 O RMII Tx enable 2 AUD_PIN_PCM_DTX 3.3 O Transmitted data of Audio PCM interface GPIO47 GPIO48 Type Description 3.0 I RMII1 Rx valid 1.8/3.
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Pin ID A79 A78 Pin name GPIO CFG. FUNC_SEL Configurable Function Voltage 0 GPIO 3.3 1 QPIC_PAD_LCD_RS_N 2 BLSP_SPI0_SS0_N(1) 3 GPIO54 GPIO61 Type Description O LCD controller RESX, reset signal. Active low 3.3 O SPI0 chip select 0 AUDIO_TD1 3.3 O Serial digital data output 1 of Audio Multi-channel I2S Tx interface and serial digital data of Audio TDM Tx interface 0 GPIO 3.3 1 QPIC_PAD_LCD_CS_N O LCD controller chip select 2 BLSP_UART0_TXD 3.
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4. Electrical characteristics TABLE 4-1. POWER SUPPLY DC CHARACTERISTICS Symbol Parameter Minimum Typical Maximum Units 3.3V Supply Voltage 3.0 3.3 3.6 V Minimum Maximum Units Storage Temperature (Commercial) -40 +70 °C Storage Temperature (Industrial) -40 +90 °C 0 +65 °C -40 +85 °C 10 90 %RH 5 90 %RH DVDD33 TABLE 4-2. TEMPERATURE LIMIT RATINGS Parameter Commercial Operating Temperature Industrial Operating Temperature Humidity Storage humidity 5. Power management 5.1.
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6. Radio characteristics 2.4GHz 802.
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7. Mechanical characteristics 4.25 5.75 43.25 49.0 45.5 5.0 3.5 3.5 5.0 45.5 43.25 5.75 4.25 1.22 1.08 10% 3.3 45.0 42.0 4.5 3.0 A 3.0 4.5 42.0 3.75 5.25 41.25 0.95 1.9 0.9 R0.45 R0.50 1 .0 R0.50 1.05 DETAIL A SCALE 8 : 1 PCB footprint 3.50 4.25 5.00 5.75 43.25 45.50 49.00 46.25 45.50 43.25 5.75 5.00 4.25 3.50 2.75 45.00 42.25 42.00 4.50 3.00 2.75 1.0 1.80 0.75 1.0 R0.5 R0.5 2.00 2.25 A 3.00 3.75 4.50 5.25 41.25 42.
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8. Design considerations 8.1. Ethernet interface ETHERNET DESIGN GUIDELINES: Category Guidelines/Remarks Groups P[0..4]_TRX[0..3]+, P[0..4]_TRX[0..3]- Route type Differential pair, 100 Ohm impedance Length < 1.5 in.
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USB 2.0 DESIGN GUIDELINES: Category Guidelines/Remarks Groups (USB2_DP, USB2_DM) and (USB1_DP, USB1_DM) Route type Differential pair, 90 Ohm impedance for the USB2.0 pair according to USB2.0 specification Return path Ensure continuous and unbroken return path without voids Length < 5 in.
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LCD DESIGN GUIDELINES: Category Guidelines/Remarks Signal/group QPIC_PAD_LCD_CS_N QPIC_PAD_CLE_LB_N QPIC_PAD_LCD_RS_N QPIC_PAD_ALE_LB_N QPIC_PAD_WE_N QPIC_PAD_OE_N QPIC_PAD_BUSY_N QPIC_PAD_DATA[8:0] Route type Single-ended 50 Ohm impedance Return path Ensure continuous and unbroken return path without voids Length < 5 in. Spacing requirements 2 W spacing to other signals GND shielding Not required Vias/layer transitions Vias are acceptable Voltage 3.3 V Voltage 3.
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8.5. SD/eMMC SDIO DESIGN GUIDELINES: Category Guidelines/Remarks Configurable function Pin name SDIO_CD GPIO22 SDIO_CLK GPIO27 SDIO_DAT[0] GPIO23 SDIO_DAT[1] GPIO24 SDIO_DAT[2] GPIO25 SDIO_DAT[3] GPIO26 SDIO_DAT[4] GPIO29 SDIO_DAT[5] GPIO30 SDIO_DAT[6] GPIO31 SDIO_DAT[7] GPIO32 Signal/group Route type Single-ended 50 Ohm impedance Return path Ensure continuous and unbroken return path without voids Length < 4.5 in.
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8.6. PCIe PCIE DESIGN GUIDELINES FOR DATA SIGNALS: Category Guidelines/Remarks Signal/group/group PCIE_TXP, PCIE_TXN PCIE_RXP, PCIE_RXN Route type Differential pair 100 Ohm impedance Return path Ensure continuous and unbroken return path without voids Length < 5 in.
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8.7. JTAG JTAG DEBUG INTERFACE DESIGN GUIDELINES: Category Guidelines/Remarks Signal/group JTAG_TRST_N, JTAG_TDI, JTAG_TDO, JTAG_TMS, JTAG_TCK, JTAG_RST_N(SRST) Mechanical Ensure sufficient clearance for placement of debug headers Spacing 2 W spacing is desirable Routing Route short (< 5 in.) and direct traces with impedance control Length match No critical requirement; recommend keeping the signals matched within 500 mils Voltage Operates at 3.
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10. Development board 10.1 DVK dimensions 10% 3.0 20.6 95.0 140.
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10.2 DVK interfaces 15 15 9 9 8 14 2 3 7 9 1 4 9 4 4 4 6 4 13 11 1. 2. 3. 4. 5. 6. 7. 8. 12 Power 12V-24V SD card socket eMMC connector Ethernet port Buttons (Reset, GPIO8) USB 3.0 (5V 1A) USB 2.0 (5V 1A) LEDs Habanero Datasheet 9. 10. 11. 12. 13. 14. 15.
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10.3 LEDs LED number Description 1 GPIO48 2 GPIO46 3 3 GPIO40 4 4 GPIO37 5 5 Power 1 2 10.4 BOOTSTRAP switch 1 2 3 4 5 JTAG_EN USB_BOOT GPIO14 GPIO51 Not connected ON GPIO0~GPIO5 are used as JTAG interface. Force boot from USB 1 1 - OFF GPIO0~GPIO5 are normal GPIOs.
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10.5 DVK header pinout J13 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 J17 Header pin GPIO Header pin GPIO Header pin GPIO 1 3.
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10.6 DVK heatsink 140.0 102.6 77.6 53.4 38.5 3.5 4x M3 Threaded 3.5 95.0 68.5 49.6 25.7 25.4 12.5 3.5 3.5 3.5 3.0 3.5 3.5 3.5 8x M2.
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11. Habanero packaging and ordering info Habanero modules are packed into trays. Each tray fits 15 modules. Every 5 trays are vacuum sealed and one standard packaging box contains 225 modules. FIGURE 12-1. HABANERO TRAY DIMENSIONS 280.0 200.0 59.3 53.4 11.5 ±0.1 10.0 ±0.1 50.6 ± 0.2 44.5 15.00 A B All Draft Angles 10° B SECTION B-B SCALE 1 : 1 41.6 46.6 ± 0.2 DETAIL A SCALE 2 : 3 280 280 FIGURE 12-2. STANDARD PACKAGING BOX DIMENSIONS 22 0 220 0 30 300 TABLE 12-3.
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12. Document Revision History Revision Revision Date 1.0 2019.08.05 Initial release. 1.1 2019.08.14 Updated mechanical and added product packaging and ordering info. 1.2 2019.09.06 Updated J18 header pin 6 description on page 28. 1.3 2020.02.06 Updated table 3-2 (page 6) and table 3-9 (page 12). Pin ID B17 to B16.
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Antenna info: 1. Type: Whip antenna Gain:2.4G :4.0 dBi 2. Type: Planare WLAN antenna Gain:2.4G :-3.6 dBi 3. 5G: Band 1: 4.5dBi, Band 4: 5dBi 5G: -5.5 dBi Type: Ceramic Antenna Gain:BT/BLE/2.4G :2.09dBi 5G: 4.
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FCC Statement This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Any Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.
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Note: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
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statements; 1. This device contains licence-exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Economic Development Canada’s licence-exempt RSS(s). Operation is subject to the following two conditions: (1) This device may not cause interference. (2) This device must accept any interference, including interference that may cause undesired operation of the device. 2.